The present invention relates to a television receiver capable of simultaneously displaying two channel images on the same screen of the television receiver.
A method for displaying images of two channels A and B on the same screen as shown in FIG. 2 is disclosed in the Japanese Published Unexamined Patent Application No. 49-2419. In the disclosed method, the image of the channel B is displayed at a right lower corner with a vertical size being approximately 1/2 of the whole vertical size of the screen, a horizontal size being approximately 1/2 and an area being approximately 1/4. A basic concept of the disclosed method lies in that samples which are sampled for every other picture element (sampling points necessary to reproduce the image) in one horizontal scan period for the channel B are stored in a memory circuit, and the content of the memory circuit is read out at a rate which is twice as high as a writing rate when a horizontal scan for the channel A sweeps an area B shown in FIG. 2. In this manner, an image signal for the channel B is displayed in the area B in FIG. 2 with the image being compressed to approximately 1/2 both vertically and horizontally.
FIG. 1 shows a specific configuration, in which numeral 1 denotes an antenna, 2 and 6 denote tuners for receiving broadcasting signals of different channels A and B, 3 and 7 denote video intermediate frequency amplifiers, 4 and 8 denote video detectors, 5 and 9 denote video amplifiers, 10 denotes a circuit for producing a vertical synchronizing signal V.sub.B and a horizontal synchronizing signal H.sub.B for the channel B, and 11 denotes a circuit for producing a vertical synchronizing signal V.sub.A and a horizontal synchronizing signal H.sub.A for the channel A. Numeral 12 denotes a flip-flop which changes its state each time the horizontal synchronizing signal H.sub.B is produced, and 13 denotes a signal selection circuit which selects one of an input signal p which is a video signal for the channel A and output signals q, r and s from a memory circuit which alternately stores signals for the channel B, depending on which one of signals C, N.sub.1, N.sub.2 and N.sub.3 is applied, to provide the selected signal at an output terminal 23. The signal selection circuit 13 operates in a manner as shown in FIG. 10. Numerals 14 and 17 denote R-S flip-flops each having a set terminal and a reset terminal and they produce output signals a and b, respectively. Numerals 15 and 16 denote counters, and 18 denotes a gated oscillator which stops the oscillation when the horizontal synchronizing signal H.sub.A is present, so that the phase of the first pulse of its output relative to the horizontal synchronizing signal H.sub.A can be maintained constant. Numeral 19 denotes a gated oscillator which produces an output signal f which has a similar relation to the horizontal synchronizing signal H.sub.B. Numeral 20 denotes a control circuit including a memory circuit for reading and writing image information and it includes circuits shown in FIGS. 5, 7, 8 and 9. Numerals 21 and 22 denote AND gates.
The oscillation frequency of the gated oscillator 18 is equal to 450 f.sub.H (Hz) when the number of picture elements in one horizontal scan period is equal to 450, where f.sub.H is a horizontal scan frequency, and the oscillation frequency of the gated oscillator 19 is equal to one half thereof, i.e., 225 f.sub.H (Hz). The counter 15 counts 525/2.times.2.div.132 pulses, when the number of horizontal scans in one field is equal to 525/2, and it sets the flip-flop 14 to cause it to produce high voltage output a when the counter 15 has counted 132 horizontal synchronizing signals H.sub.A. The counter 15 and the flip-flop 14 are reset by the vertical synchronizing signal V.sub.A. The counter 16 counts 450/2=225 pulses when the number of picture elements in one horizontal scan period is equal to 450. When the counter 16 has counted 225 output pulses of the gated oscillator 18, it sets the flip-flop 17 so that the output b assumes a high voltage state. The counter 16 and the flip-flop 17 are reset by the horizontal synchronizing signal H.sub.A. With this arrangement, when the area B shown in FIG. 2 is swept, the outputs a and b are at the high voltage state so that the output e of the AND gate 22 produces the output of the oscillator 18.
A broadcasting signal for the channel A, as shown in FIG. 4A, received by the tuner 2 is applied to the signal selection circuit 13 as the video signal p through the circuits 3, 4 and 5. A broadcasting signal for the channel B received by the tuner 6 is applied to the control circuit 20 through the circuits 7, 8 and 9. The control circuit 20 includes three analog memories each comprised of CCD or BBD and a control circuit for sequentially driving the analog memories. As shown in FIG. 4B, the control circuit 20 samples a video signal v and stores the samples in different analog memories for each field. The signals stored in the analog memory which has completed the writing are read out at a rate which is twice as high as the sampling rate. As a result, a video signal having a time axis compressed to 1/2 as shown in FIG. 4C is produced. Those video signals appear for each field as the signals q, r and s. The signal selection circuit 13 appropriately selects the signals p, q, r or s so that a video signal which is a combination of the video signals for the channel A and the channel B as shown in FIG. 4D and which corresponds to the image shown in FIG. 2 is produced at the terminal 23.
The circuits included in the control circuit 20 are shown in FIGS. 7 to 9. FIG. 7 shows a ring counter. Starting from any state of flip-flops FF.sub.1, FF.sub.2 and FF.sub.3, when the vertical synchronizing signal V.sub.B triggers the flip-flops FF.sub.1 to FF.sub.3 a predetermined times, outputs M.sub.1, M.sub.2 and M.sub.3 repeat an output state shown in FIG. 11 each time the synchronizing signal V.sub.B is received. The outputs M.sub.1, M.sub.2 and M.sub.3 are used as the signals to select a write circuit. FIG. 8 shows a circuit which produces signals N.sub.1, N.sub.2 and N.sub.3 from the signals M.sub.1, M.sub.2 and M.sub.3 derived from the circuit shown in FIG. 7, the signal a and the synchronizing signal V.sub.a. The signals N.sub.1, N.sub.2 and N.sub.3 are used as the signal to select a read circuit and as the signal to select one of the signals p, q, r and s by the signal selection circuit 13.
FIG. 9 shows a circuit for producing a writing clock or a reading clock for the read and write circuits by selecting one of the output e of the oscillator 18 through the AND gate 22 and the output f of the oscillator 19 by the signals M.sub.1, M.sub.2, M.sub.3, N.sub.1, N.sub.2 and N.sub.3.
FIG. 5 shows the memory circuit included in the control circuit 20 and a circuit for writing the image information into and reading it from the memory circuit. Numeral 206 denotes the memory circuits and 205 denotes a shift register. Blocks 502 and 503 have the same configurations as a block 501. The block or circuit 501 receives the signals M.sub.1, N.sub.1 and U.sub.1 while the circuits 502 and 503 receive M.sub.2, N.sub.2 and U.sub.2, and M.sub.3, N.sub.3 and U.sub.3, respectively. When (M.sub.1, M.sub.2, M.sub.3)=(1, 0, 0), the information is written in the circuit 501, when (M.sub.1, M.sub.2, M.sub.3)=(0, 1, 0), it is written in the circuit 502, and when (M.sub.1, M.sub.2, M.sub.3)=(0, 0, 1), it is written in the circuit 503. When (N.sub.1, N.sub.2, N.sub.3)=(1, 0, 0), the circuit 501 is read, whne (N.sub.1, N.sub.2, N.sub.3)=( 0, 1, 0), the circuit 502 is read, and when (N.sub.1, N.sub.2, N.sub.3)=(0, 0, 1), the circuit 503 is read. As seen from FIG. 8, M.sub.i is not equal to N.sub.i (M.sub.iA .noteq.N.sub.i). In the read and write operations of the circuit 501, when M.sub.1 =1, AND gates 201 and 203 are opened and AND gates 202 and 204 are closed. Accordingly, a first stage flip-flop of the shift register 205 is set by the synchronizing signal V.sub.B while the flip-flops of the other stages are reset. That is, the shift register 205 assumes a state 100 . . . 0. As the signal d is received, the state changes to 010 . . . 0, thence to 0010 . . . 0. The signal U.sub.1 is equal to the output f of the oscillator 19 and it provides write clocks .phi..sub.1 and .phi..sub.2 to the memory circuit 206. Since the signal d shifts the shift register 205 for every other horizontal scan of the synchronizing signal H.sub.B, the information for every other horizontal scan is stored in each memory circuit. Symbol v denotes the video signal. When N.sub.1 =1, the AND gates 201 and 203 are closed while the AND gates 202 and 204 are opened. In this case, the shift register 205 is set by the signal V.sub.A to a state 100 . . . 0, and as the signal H.sub.A is received, the state is changed to 0100 . . . 0, thence to 0010 . . . 0. The signal U.sub.1 is equal to the output e of the AND gate 22 and it provides read clocks .phi..sub.1 and .phi..sub.2 for the memory circuit 202. The reading rate is equal to the oscillation frequency of the oscillator 18.
FIG. 3 shows a relation among the vertical synchronizing signal for the channel A, the vertical synchronizing signal for the channel B, and the read and write of the image information for the channel B. A signal portion B.sub.1 is written in the circuit 501, a signal portion B.sub.2 is written in the circuit 502 and a signal portion B.sub.3 is written in the circuit 503, and they are read at the corresponding number areas shown on the channel A signal. On the right side of each broken line, the horizontal sweep is carried out in the area B shown in FIG. 2.
FIG. 6 shows a configuration of the memory circuit. The shift signals .phi..sub.1 and .phi..sub.2 are square wave and out-of-phase. V.sub.1, V.sub.2 and V.sub.3 denote voltages at capacitors C.sub.1, C.sub.2 and C.sub.3, respectively. U.sub.k denotes a sample of a signal. When a base voltage of a transistor reaches a voltage U, it starts to conduct and a current flows from the capacitor immediately succeeding thereto until the capacitor in the preceding stage is charged to the voltage U. The voltage at that stage momentarily reaches 2U and the charge is moved until the voltage reaches U+U.sub.k. Therefore, the information contained in that stage is transferred to the succeeding stage. G denotes a gate signal.
The description thus far explained is directed to the display of the image of another channel at the right lower corner of the screen of the television receiver at the size compressed by the factor of 2 both vertically and horizontally. The size of the compressed image can be changed by changing the count capacities of the counters 15 and 16 and replacing the flip-flop 12 with a counter having an appropriate count capacity. The display position need not be limited to the right lower corner but it may be displayed at the right upper corner, left upper corner or the left lower corner.
In this manner, the image for the sub-channel can be displayed on a portion of the image for the main channel, but depending on the images displayed, it is difficult to distinguish the images for the two channels from each other and a viewer may feel obstacle sense.